Connector and pad reference#

Use these tables to find a signal, check a connector pin or lay out a mating board. Pad numbers and net names follow the KiCad PCB. Each row represents one electrical pad number on one connector. Check the connector locator and key before wiring: a cable-face view can reverse the apparent pin order.

J3 — left expansion row#

Board side: F.Cu. Use the board views and connector key for orientation.

Pad	PCB net
1	`GND`
2	`PA19`
3	`PA15`
4	`VAA`
5	`PB12`
6	`INT`
7	`PB21`
8	`PB22`
9	`BSL_I2C_SCL`
10	`BSL_I2C_SDA`
11	`+5V`
12	`GND`

J4 — Qwiic#

Board side: F.Cu. Use the board views and connector key for orientation.

Pad	PCB net
1	`GND`
2	`+3.3V`
3	`BSL_I2C_SDA`
4	`BSL_I2C_SCL`
5	`no assigned net`
6	`no assigned net`

J6 — right expansion row#

Board side: F.Cu. Use the board views and connector key for orientation.

Pad	PCB net
1	`GND`
2	`CANL`
3	`CANH`
4	`+5V`
5	`AN`
6	`PA20`
7	`PA21`
8	`PC2`
9	`PC4`
10	`PC6`
11	`+3.3V`
12	`GND`

J2 — debug row#

Board side: F.Cu. Use the board views and connector key for orientation.

Pad	PCB net
1	`3.3VIN_DEBUG`
2	`PA13`
3	`PA14`
4	`BSL_UART_TX`
5	`GND`
6	`BSL_UART_RX`
7	`nRST`
8	`BSL_INVOKE`

J5 — CAN bus#

Board side: F.Cu. Use the board views and connector key for orientation.

Pad	PCB net
1	`+5V`
2	`CANH`
3	`CANL`
4	`GND`
MP1	`no assigned net`
MP2	`no assigned net`

J1 — LGA module interface#

Board side: B.Cu. Use the board views and connector key for orientation.

Pad	PCB net
A1	`PA4`
A2	`PA2`
A3	`BSL_UART_TX`
A4	`PB3`
A5	`PB0`
A6	`PC25`
A7	`PB13`
A8	`PC5`
A9	`PC3`
A10	`PC1`
B1	`BSL_INVOKE`
B2	`PA5`
B3	`PA3`
B4	`PC18`
B5	`PB1`
B6	`PC26`
B7	`PB14`
B8	`PC4`
B9	`CAN_TERM`
B10	`PA25`
C1	`PA16`
C2	`PB5`
C3	`BSL_UART_RX`
C4	`INT`
C5	`nRST`
C6	`PB15`
C7	`PC6`
C8	`PC2`
C9	`PA24`
C10	`BSL_I2C_SCL`
D1	`PA18`
D2	`PB4`
D3	`PA7`
D4	`GND`
D5	`+VDC`
D6	`GND`
D7	`+VDC`
D8	`PA20`
D9	`BSL_I2C_SDA`
D10	`PA21`
E1	`PC8`
E2	`PC7`
E3	`PA17`
E4	`+VDC`
E5	`GND`
E6	`+VDC`
E7	`GND`
E8	`PB22`
E9	`PA19`
E10	`PB23`
F1	`PC10`
F2	`PC11`
F3	`PC9`
F4	`GND`
F5	`VAA`
F6	`GND`
F7	`+VDC`
F8	`PB21`
F9	`PB19`
F10	`PB20`
G1	`PC12`
G2	`PC13`
G3	`PB25`
G4	`+VDC`
G5	`GND`
G6	`+VDC`
G7	`GND`
G8	`PB10`
G9	`PB18`
G10	`PB17`
H1	`PC14`
H2	`PC15`
H3	`PA27`
H4	`PB26`
H5	`PB29`
H6	`PB6`
H7	`PB16`
H8	`CAN_TX`
H9	`PB12`
H10	`PB11`
J1	`PA26`
J2	`PA29`
J3	`PA31`
J4	`PB28`
J5	`PB31`
J6	`PB8`
J7	`PA8`
J8	`PA10`
J9	`PA14`
J10	`PA15`
K1	`AN`
K2	`PA30`
K3	`PB24`
K4	`PB27`
K5	`PB30`
K6	`PB7`
K7	`PB9`
K8	`PA9`
K9	`CAN_RX`
K10	`PA13`

Using the pad table#

The top and underside board views show the viewing convention.

For alternate peripheral functions on each MCU pad, use the interface cheat sheet. The table here describes the physical wiring, including PC0 on CAN_TERM at J1.B9 and the separate PB9 connection at J1.K7.

The downloadable CSV contains the same unique pad assignments and board sides. Separate connectors and different pad numbers remain separate even when they share a net. A net marked unconnected has no signal connection at that pad. Mechanical pads appear too, since some connect to power or ground.

Download pad CSV